Assertion based verification tools

Questa simulation spans all levels of design and verification abstraction and supports multiple verification methodologies and languages to increase testbench productivity, automation and reusability. Questa Design Solutions is an automated and integrated suite of verification tools that analyzes code at the design stage to detect bugs early, where they are cheapest and easiest to fix. Questa Formal verification apps boost verification efficiency and design quality by exhaustively automating verification tasks that are difficult to complete without requiring formal or assertion-based verification experience.

Questa Verification IP improves quality and reduces schedule times by building protocol and methodology reusable components that support many industry standard interfaces. Extends the Questa Verification platform to the mixed-signal world for the creation and verification of complex analog and mixed-signal designs.

Smart systems are ubiquitous and many are safety-critical, so developers must be able to detect and control failures.

Developers need high performing tools to perform safety analysis and fault simulation with safety mechanisms. These are the areas where equivalence checking is commonly used. Another point to note here is, Equivalence Checking is always carried out using two inputs and result comes out by comparing the functionality of these two input designs. Combinational and sequential equivalence checking are the two methods used nowadays.

Combination Equivalence checking is done by making one-to-one mapping of flops between golden design and revised design. But Sequential equivalence checkers can verify structurally different implementations which do not have one-to-one flop mapping. Formal Property Checking Formal property checking is a method to prove the correctness of design or show root cause of an error by rigorous mathematical procedures.

It does not require test benches or stimuli and turnaround time is very less. SVA is the assertions subset of the System Verilog language. Assertions or properties are primarily used to validate the behaviour of a design and can be checked statically by property checker tool and proves whether or not a design meets its specifications.

Formal Verification compared with Simulation Even if modern test-bench concepts allow for flexible and efficient modeling and sophisticated coverage analysis, Functional verification by simulation is still incomplete, causes high efforts in test-bench design and consumes a deal in simulator run-time.

In addition, experience has shown that formal techniques not only improve verification quality, but also can reduce the verification effort and time and also a quick and thorough module verification. There are ways to cope with such issues. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs.

Citation Context DATE, We present results of using GoldMine for assertion generation of the RTL of a core processor de We present results of using GoldMine for assertion generation of the RTL of a core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.

It is increasingly difficult to guarantee the first silicon success for complex integrated circuit IC designs. Post-silicon validation has thus become an essential step in the IC design flow. Abstract - Cited by 4 3 self - Add to MetaCart It is increasingly difficult to guarantee the first silicon success for complex integrated circuit IC designs.

Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers. In this paper, we provide in-depth discussion for trace-based debug strategy and review recent advancements in this important area.

When searching for functional bugs in silicon, debug data is acquired after a trigger event occurs. A trigger event can be configured at run-time using a set of control registers that uniquely identify the event that initiates data acquisi-tion. Nonetheless the values loaded in these programmable re Abstract - Cited by 4 3 self - Add to MetaCart When searching for functional bugs in silicon, debug data is acquired after a trigger event occurs.

Nonetheless the values loaded in these programmable registers interact only with a set of pre-defined trigger sig-nals that are selected at design-time. If the state conditions required for triggering cannot be expressed directly in terms of the pre-defined trigger signals, the common practice is that the designer manually searches for an equivalent trig-ger event that can be programmed on-chip.

In this paper we investigate if trigger events can be automatically generated from a set of state conditions. Trace-based debug solutions facilitate to eliminate design errors escaped from pre-silicon verification and have gained wide acceptance in the industry. Meanwhile, even trained SVA users often say that they find the language difficult to work with, both for coding and debug. Verification engineers also complain that composing temporal SVA assertions is especially challenging.

The flexibility of off-the-shelf assertions is arguably an extension of the coding issue, but still merits consideration in its own right. The OVL provides a set of standard assertions for common use-cases, but the increasing complexity of subsystem and system design has led to ever greater complaints that they lack an ability to be customized to meet rapidly changing design intent requirements.

The same is said of the assertion libraries provided by vendors which, though more regularly updated, are also engaged in trying to keep up with the design landscape, particularly as consumer devices require ever increasing functionality. Customization — and the subtleties it therefore requires — again stresses the need for design and verification teams to maintain sufficient local expertise in assertion languages. Any assertion process must have a structured way of reporting and tracing errors, a working coverage database, and techniques that allow for thorough ongoing analysis both within and across projects, as well as a tightening of the integration between simulation, emulation and verification.

ABV must not simply do its job but also be seen and acknowledged to have done its job, if the technique is to gain currency within the user company. In a DAC Accellera workshop, Harry Foster of Mentor Graphics suggested four questions that companies should ask themselves to assess how well they were balancing the benefits of and challenges with assertions, and whether they were fostering the right strategy for their use:.

The leading tool vendors now provide ABV methodology structures within their simulation, verification and emulation software suites.

There have also been a number of useful attempts to produce software that automates the generation of assertions or makes SVA easier to compose by using a graphical environment. Users can leverage all of these technologies to gain great benefits from assertions and ABV. But even as more and more companies claim to use the technique, there remain many who use assertions on an as you go basis believing they are operating ABV, but still lacking a true methodology.

Others have methodologies which could be made more effective. Assertions are often thought of as a technique that is used to get a design right before it is committed to silicon.

Careful design of the assertions can improve the controllability and observability of your logic design, making it easier to find deeply buried bugs during post-silicon validation.

What are assertions?